iRADAnalyzer 1. Functional Description
R34US0001EU0200 Rev.2.00 Page 2 of 18
Oct 18, 2022
1. Functional Description
The RHADC-FMCEV1Z motherboard is intended to operate with the iRADAnalyzer software along with a
radiation hardened precision SAR ADC evaluation board (daughterboard). The motherboard collects digitized
data from the daughter board ADC and relays that data to a PC running iRADAnalyzer so the data can be
analyzed for performance.
1.1 Hardware
There are two components in the hardware portion of the evaluation platform: the RHADC-FMCEV1Z
motherboard and the ADC daughter card (Figure 1
). The ADC is contained on the daughter card that contains the
analog input and clock circuitry. The daughter card interfaces with the motherboard through a High Pin Count
(HPC) FPGA Mezzanine Connector (FMC). The daughter card was designed to be compatible with the Vita 57.1
standard. The motherboard contains a USB interface, an FPGA, and four banks of SDRAM. The motherboard
serves as the interface between the host PC and the ADC daughter card. The daughter cards have jumpers that
set the operating voltages. The FPGA accepts output data from the ADC and buffers it in the SDRAMs before
passing it to the PC at a lower speed for post-processing. The maximum buffer depth is 32 Megawords (225),
however, the evaluation software is capable of processing data records only up to 1 Megaword (220) deep. If
usage of the full 32 Megaword depth is required.
You must supply the low-jitter analog signal generators for the clock and analog inputs to operate the daughter
card. Recommendations of suitable generators can be found in Appendix
: Analog Signal Generators. Many low-
jitter analog signal generators exhibit high harmonic spectral content relative to the ADC performance. A band-
pass filter is recommended to attenuate the harmonics.
1.2 Daughter Card
The daughter card is designed to produce optimal ADC performance and simplify the evaluation process. Some
boards have multiple connections for the analog input and clock.
1.2.1 Daughter Card Compatibility with FMC Host Cards
The daughter card connects to the motherboard through a High Pin Count (HPC) FPGA Mezzanine Connector
(FMC). The daughter card was designed to be compatible with the Vita 57.1 standard. This is intended to facilitate
the use of the daughter card with commercially available FMC host cards. These generators provide low jitter to
optimize the SNR performance of the ADC under test. Other generators with similar phase noise performance can
also be used. Contact Renesas Technical Support
for recommendations. Signals described as being sourced by
the Host must be provided by the FMC host card to the daughter card. These signals are necessary for the
daughter card to be fully functional. Signals described as being sourced by the daughter card are provided by the
daughter card to the host card. These signals can be optionally ignored by the host card if the functionality they
provide is deemed unnecessary.
1.3 Motherboard
The only connections required for the motherboard are a +5V power supply and a USB connection to the PC
running iRADAnalyzer. No additional configuration of the motherboard is required.
1.4 Software
The software component is iRADAnalyzer, a Graphical User Interface (GUI) created with Java. The GUI reads
data from the motherboard, optionally post-processes the data (FFT analysis), and displays the results. Data can
be viewed in the time or frequency domain and can be saved for processing later. Critical performance
parameters such as SNR, SFDR, and harmonic distortion are calculated and displayed on-screen when viewing
in the frequency domain.